Large scientific simulations usually demand both much memory and high speed. To supply that, some supercomputers of the vector type and parallel computers of the multiprocessor type have been developed in last two decades. Since the vector computer itself almost reaches the acme of development, it is expected that some systems with a number of vector processors or a lot of scalar processors or ones of the mixed type will form the next generation of supercomputers. Today we already have systems with several vector processors and a vast shared storage of many memory banks, but they are only an extension of conventional vector machines and rely on the idea of dividing a simple long vector into several parts to be computed by many pipelines. On the other hand, current parallel computers of the multiprocessor type mostly use the distributed memory system, and they use anyone of three types of network to transfer data among processors: the grid, the hyper-cube and the hyper-cross network type. The first has been used from the early stage, but it is not so hopeful due to problems in data transfer ability. The second, the hyper-cube network, was well appreciated until quite recently in the U.S., and it supplies more data transferring ability than the first. But its whole system generally assumes an inhomogeneous scheme of transfer, which cannot help reducing its performance. The last, the hyper-cross-network, is very powerful in allowing uniform data transfer among processors and therefore giving us a simple scheme of data passing. It was proposed by the same applicant and we already have its realization as a practical powerful machine (ADENART provided by Matsushita Electric Industrial Ltd.). That system with distributed storage and network, however, produces more or less overhead of data transfer, which diminishes its performance.
The new system replaced the buffer memories placed at all cross point nodes of the hyper-cross-network as seen in the previous system with the memory banks on those nodes, which constitute the main storage and allow three ways and an auxiliary way to access them. Those ways assure the full ability of the previous system with no overhead due to data transfer and hence allow to get a very high sustained performance.
Today's supercomputers with several vector units are supplied with a common memory array of banks, usually being accessible from all vector units, but they could not have many more vector units because it would become hard to secure sufficient access ways to many banks without any bank conflict. On the other hand, the new system of this invention allowed vector units only to access partial banks in the regular scheme from the outset. The scheme is based upon the concept of ADEPS(Alternating Direction Execution of `Parallel over Segments`) common to the whole family of parallel computers devised by the same applicant.